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The Architectures LDRD group focuses on evaluating and profiling key NERSC codes and their performance on current and future supercomputing architectures. In addition to porting codes to these systems, the Architectures LDRD uses analytic models and simulations to predict how future HPC architectures will perform, and to determine how best to optimize NERSC codes on specific platforms.
Architectures LDRD Participants
- Paul Hargrove
- Kathy Yelick
- Leonid Oliker
- Eric Roman
- Parry Husbands
- John Shalf
- Shoaib Kamil
Architectures LDRD Papers
- Evaluation of Architectural Paradigms for Addressing the Processor-Memory Gap
Submitted to HPCA-10
L.Oliker, P.Husbands, G.Griem, J.C.Lawrence | PDF
- Identifying Performance Bottlenecks on Modern Microarchitectures using an Adaptable Probe
3rd International Workshop on Performance Modeling, Evaluation, and Optimization of Parallel and Distributed Systems (PMEO-PDS), 2004, to appear.
G.Griem, L.Oliker, J.Shalf, K.Yelick | PDF
- Transitive Closure on the Imagine Stream Processor
Fifth Workshop on Media and Stream Processors (MSP5) 2003.
G.Griem, L.Oliker | PDF
- Performance Evaluation of Two Emerging Media Processors: VIRAM and Imagine
Workshop on Parallel and Distributed Image Processing, Video Processing, and Multimedia (PDIVM) 2003.
S.Chatterji, M.Narayanan, J.Duell, L.Oliker | PDF
- Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
International Parallel & Distributed Processing Symposium (IPDPS) 2002.
B.Gaeke, P.Husbands, X.Li, L.Oliker, K.Yelick, R.Biswas | PDF
Download BibTex
entries for the above papers here.
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